Peak detecting and reshaping circuit



June 1, 1965 SUNG PAL CHUR 3,187,199

PEAK DETECTING AND RESHAPING CIRCUIT I Filed Jan. 5l, 1962 2Sheets-Sheet 1 LIT/L IZA TION NE TWORK YTOPA/Ey June l, 1965 SUNG PALCHUR 3,187,199

PEAK DETECTING AND RESHAPING CIRCUIT Filed Jan. 31, 1962 2 Sheets-Sheet2 FASE DP/VE 70 neA/vs/srae I I /O +I v w o.,

k I I CMPP/NG B/As BASE .DR/v5 7a /5 I reANs/sroz I u +/1/ o OV I' I ITRANS/$7292 35 I I I I cascro2 l I k CURRENT I I I I I (C) g4 6/ f s I ul l l ac. BASE .esl-7 I o: rRAA/s/sroe |64 I I l l +.6v--- ()$+.25v-- II I I E BASE vra/.use s #g55/05%? I l I 4 l l I cc/ scrgg l i I I 4reAA//csme 67 l 1 5% n (s) u g 7/ME :II-I IE! SUA/6 P, CHUR IN1/15mmATTORNEY United States Patent O 3 187,199 PEAK DETECTENG ND RESHAPINGCIRCUIT Sung Fal Chur, 1Los Angeles, Calif., assigner to ArupexCorporation, Redwood City, Calif., a corporation of @alifornia Filed.lan 3l, 1962, Ser. N 17%,l17 5 Claims. (til. 307-885) This inventionrelates generally to peak detector circuits and particularly relates toa transistor circuit for clipping the peaks of the read-out signalobtained from a moving magnetic storage medium and for developing sharpoutput pulses.

It is conventional practice in the digital computer art to store binaryinformation on a moving magnetic medium such as a drum or tape. It ishighly desirable to be able to pack the binary digits as closely aspossible on the magnetic storage medium to save space. It is equallydesirable to read out previously stored information as tast as possiblewithout losing information or without obtaining erroneous read-outsignals.

Binary information may be recorded with high density on magnetic tapesor the like by modern systems. Greater technical problems usually residein obtaining a readout signal that is free from error or ambiguity. thepeaks of the output wave derived from the magnetic read head associatedwith fthe magnetic medium must be clipped to discriminate against noisewhich causes voltage variations of a lesser amplitude than thoserepresenting a binary signal. Furthermore, these clipped eaks no longereven resemble a pulse of the type required a digital system.Consequently, the clipped voltage peaks must be converted to sharppulses having a leading edge which corresponds to the peak of thevoltage wave.

ln the non-returnto-zero method of recording binary information on amoving magnetic medium the read-out signal has both positive andnegative voltage peaks. For this recording method a clipper and peakdetector circuit must be devised which will clip voltage peaks of eitherpolarity and develop sharp output pulses having a leading edge whichcoincides in time with the peak of the read-out voltage wave.

It is, accordingly, an object of the present invention to provide animproved peak detector which is particularly suitable for reshaping theread-out signal derived from a moving magnetic medium into output pulsessuit# able for use in a digital computer.

Another object of the present invention is to provide a clipper circuitwhich will clip voltage peaks of either polarity.

A further object of the invention is to provide a relatively simple andreliable transistor circuit suitable as a peak detector and pulseShaper.

In accordance w'th the present invention there is provided a transistorcircuit having clippers with adjustable clipping bias to respond toamplitude peaks of either polarity. The clippers are followed by anamplifier developing an output current representative of the clippedpeaks. The amplifier is followed by a differentiating circuit whichdevelops an output voltage proportional to the rate of change of theoutput current and which preferably consists of one or more inductorshaving a damping resistor connected in parallel. The output voltage ofthe differentiating circuit is a voltage wave having rst one polarityand [then rapidly changing to the opposite polarity.

Means are provided for developing Van output pulse" having a leadingedge which coincides in time `with the zero crossing point ofthedifferentiated voltage Wave. This zero crossing point is substantiallyidentical with the peak of the read signal derived from the moving Thusalertas magnetic medium, and hence the circuit assures proper timing ofthe output pulses. The circuit may also include one or two amplifierstages for the differentiated voltage and an output stage which isnormally cut off and begins to conduct current when the diderentiatedvoltage wave crosses the zero point, thus generating an output pulsewith a leading edge occurring at the desired instant of time.

These and other objects of the present invention will be betterunderstood from the following description, taken in connection with theaccompanying drawing, in which: v

FGURE l is a' circuit diagram of a transistor circuit embodying Ithepresent invention; and

FIGURE 2 is a graph of various voltage and current waves occurring intheoperation of the circuit of FG- UREV 1 and plotted as a function oftime. Y

Referring now to the drawing and particularly to FIG- URE l there isillustrated a peak detector and pulse Shaper embodying the presentinvention. The circuit of FIGURE l includes two transistors lil and 1lwhich may be PNP junction transistors as indicated by their symbols. Thetwo transistors l@ and ll form a voltage clipper for clipping both thepositive and negative peaks of an input wave applied in push-pull orout-of-phase relationship toV two input terminals l2 and i3. The twoout-of-phase input waves M and l5 which are applied to input terminalsl?. and l respectively are illustrated in FIGURE 2. The out-of-phaseinput waves may be obtained by a conventional phase splitter such asl anamplifier having unity gain which inverts the polarity of an input waveso as to provide two waves which are mirror images, relative to selectedbase lines (the +1 volt lines in the two curves of FGURE 2).YV Bothtransistors lil and lll are connected inV the grounded collectorconfiguration and accordingly the collectors of both transistors aredirectly connected to a source of negative voltage schematicallyindicated at E6. One'input terminal l2 is connected to the base oftransistor lo by a coupling capacitor l? and similarly the base of theother transistor il is connected to the remaining input terminal 13 by acoupling capacitor 18. The emitter of the iirst transistor l@ isconnected by series-coupled resistors 20 and 2l to a positive source ofvoltage schematically indicated at 22. The emitter of the secondtransistor ll is connected to the positive voltage sourcerZ?. throughseries-coupled resistors 23 and 2l. Accordingly resistor 2l is common tothe emitter circuits of both transistors 'lil and il, through resistors26 and 23; An adjustable source of clipping bias level is coupled tosupply both transistors l@ and ll with a clipping bias. To this endthere maybe provided a source of voltage 25 having its negative terminalgrounded. Aresistor 25 is connecaed across the source 25 and is providedwith an adjustable tap 27 to supply an adjustable bias voltage. Thisclipping bias is applied to the junction between two resistors 2d and 3?connected between the bases of transistors lil and ll. In a manner whichis more fully explained below, the two transistors l@ and il are biasedso as Ato be normally nonconducting inthe absence of an input signal.

The clippers l@ and ll are followed by another PNP junction transistor35; The

nected to a ground lead 36. The emitter of transistor 35 is connected bylead37 to the junction of the resistors23, 21. Accordingly, it will. beseen that the emitter cur- Y rents of the three transistors lil, 11 and35 all flow through resistor 21. The through a load .inductor 3S tothenegative 'voltage source 16. V

The transistorz is 'followed by a transistor stage f transistor 35 isconnected Vin` the grounded base configuration, withits base directlycon-f collector of transistor 35 is connected,

which is connected in the grounded collectonemitter followerconiiguration. Therefore the collectorr of transistor 40, which may bethe PNP type, is directly connected to the negative voltage source 16.VThebase of the emitter follower transistor 40 is coupled to thecollector of transistor 35 by a direct-current blocking capacitor 42which has a negligible impedance at the signal frequencies, and thetransistor 40 conducts at all times. The base of transistor 4t) isgrounded through an inductor 43 connected in parallelwith a dampingresistor 44. 'The inductors 38 and 43 in conjunctionwith the resistor 44Vform a current-tovoltage differentiating network as will be more fullyexplained hereinafter.

e The emitter of transistor 40 is connected tothe 'positive voltagesource 22 through a load resistor 45.; Furthermore the emitter oftransistor 40 is directly connecte-.dto the base of a transistor 41which forms a differential pair in conjunction with another transistor50. The emitters of transistors 41 and 50 are also connected' to thepositive voltage source 22 through a load resistor 46. Thus thetransistorsr41 and 50 may be considered as an amplifier stage for thedilierentiated signal impressed on the base of the transistor 40 ,whichemerges at its emitter. v

The grounded-base-coupled transistor 50 in the differential pair forms apulse generator or shaper and may also be a PNP junction transistor asshown. Therefore, a voltage divider network consisting of resistors 51and 52 may be connected between and the ground lead 36. The junctionpoint of resistors 51, 52 is connected to the base of transistor 50. Theemitter of transistor 50 is directly tied to the emitter of transistor41 so that the emitter currents of both transistors flow throughresistor 46. An output load impedance such as resistor 53 is connectedbetween the collector ot transistor 50 and the negative voltage source16 to develop output pulses. The output pulses may be obtained fromoutput terminal 54 and may then be fed to a utilization network. As isexplained inV more detail below, transistor 50 is biased so as to benormally non-conducting. Thus transistor 5i) does not conduct currentunless the base of transistor41 is driven more positive than that of 50.

It will be understood thattransistors 10, 11, 35, 40', 41 and 5t) may bereplaced by NPN junction transistors. VIn that case the polarityY of thevoltage sources should be reversed and the circuit `will otherwiseroperate inr essentially the same manner except that the polarity of theoutput pulses is reversed.

The circuit of FIGURE 1 operates in the following manner. It should benoted that the emitter currents of the three transistors 10,11 and 35all ilow through the common emitter resistor 21. Y The emitterV currentVof transistor flowsthrough resistor 20 and that oftransistor `11 .tiowsthrough resistor v23. The emitter current of transistor 35 flows onlythrough emitter resistor 21. Since the base of transistor 35 is directlyconnected to ground and the emitter thereof is connected throughresistor 21to the positive voltage source 22 and hence is heldV at somepositive voltage, the transistor 35 is normally tors 10 and 11 arebiased by the clipping bias to +1.0 volt and since the emitter-to-basevoltage drop is assumed to about 0.25 volt, the transistors 10 or 11will begin to conduct current when the input wave applied thereto isnegative going and approaches 0 volt. As, shown in FIGURE 2 input wave15 iirst becomes negative at the shaded Wave portion 60. When the ypartof the wave which is represented by the shaded wave portion 60 occurs,the transistor 11, to which this Wave is applied, becomes conductive.Because the current through common emitter resistor 21 remainssubstantially constant, the current through transistor must be reduced,causing a corresponding decrease in its collector or output current.This is shown at 61 in FIGURE 2 as the collector current waveV oftransistor 35. Similarly when the input wave 14 becomes negative asshown byshaded curve portion 62 the other clipper transistor 10beginsto'conduct current. As a result the collector current of transistor 35is reduced again as shown by curve portion 63.V It will be observed thatminor variations of the input waves which may be caused by noise areclipped oit by the clipping bias and cause no Yvariations in thecollector current of transistor 35. The circuit parameters of the threetransistors 10, 11

A and 35 are so selected that transistor 35 always conducts the positivevoltage source 22A t current and is not saturated or cut ofr. As aresult the clipped peaks of the input wave are faithfully reproduced asshown at 61 and 63. s

The output. impedance as seen by the collectorrof tranc sistor 35 isessentially the inductance of inductors 38 and conductive because Ya PNPtransistor conducts current" when its emitter is positive withrespect toits base.

The `voltage drop of transistor 35 between its emitter and base may beassumed to be about.0.25 volt. Hence the i emitter of transistor 35 isnormally about 0.25 volts posit tive.' Assume here that the clippingbias appliedto the bases of transistors 10 and 11 through the adjustablearm is 1.0volt positive. Accord-- ingly, in the absence of an inputsignal both transistors 10 and 11 arecut oit'. As long as the emitter oftransistor 35 is at +0.25 volt, the emitters of transistors 10 and 11lare alsoat that voltage. Because their bases are at +1.0 volt theycannot conductcurrent because their emitters arek negative with respectto their bases.

Assume now that the out-of-phaseY input waves 27 of the potentiometer 2614 and i 15 shown in FIGURE 2 are applied to the two input terminals 12and 13 respectively. s Since the bases of transis- 43, the resistance.of resistor 44 and the input impedance of transistor 40, allbeingconnected in parallel. The impedance of the blocking capacitor 42 at thesignal frequencies is so small that it can be ignored. The inductors 38,43 and the resistor` 44 form a differentiating circuit which develops anoutput voltage corresponding to the rate of change of thercollectorcurrent. The resistor 44 may furtherbe considered a damping resistor todampen the voltage swing across thev inductors 38 and 43.

Thus the voltage impressed on the base of emitter follower transistor 40corresponds essentially to the rate of change of .the collector currentoftransistor 35 which is very closely proportional to the rate ot changeof the voltage of the clipped waveform such as 60 and 62 of the inputwave.` Consequently, the voltage developed across the inductors 43 and.38 is essentially the time derivative of -the clipped input voltage.The refe-rence zero crossing of the voltage appearing at the base oftransistor 40 `corresponds very closely to the clipped peaks of theinput voltage.. This positive-going zero crossing of` the timederivative voltage is now detected substantially without time shiftthrough amplifier transistors 41 and 50.

The base of the emitter follower transistor 40 is essentiallylat groundpotential in the absence of a signal since the resistance .of inductor43 is negligible. The resistor 45- maintains the emitter of transistor40 at about +0.25 volt., Transistor 40, as an emitter-follower has ahigh input impedance and low output impedance with approximately unityvoltage. gain.l The voltage divider consisting of resistors 51 and 52has a low impedance and is proportioned to maintain the base oftransistor 50 at about +0.60 volt, that is, about 0.35 volt morepositive than the base of transistor 41 which is at +0.25 volt, the samepotential as the emitter of transistor 40 to which it is tied. Theemitters of both transistors 41 and 50 may be heldat about` +0.50 volt-by Iresistor 46. As a result under static conditions transistor 41 isconductive while transistor 50i is cut oit. For transistor 41 tlheemitter is positive'with respect to its base while the base oftransistor 50 is more positivethan its emitter.

The differentiated wave form 64 appears at the base of transistor V41with the same polarity as the Wave impressed on the base of transistor40. The wave 64vhas a negative port-ion 65 and a .positive portion 66separated by the zero crossing of the wave.. The negative wave portion65 correspondsto the collector current decrease of 55 transistor 35 asshown by current wave 61 while the positive portion 66 corresponds tothe increase of collector current wave 61. PIhus Vwhen the base oftransistor 41 becomes more positive, the emitter of transistor Si? inthe differential pair follows. Eventually the emitter of transistor Stibecomes more positive than its base which was held at +0.60 volt andtransistor 5t? begins to conduct current.

The resulting voltage drop across load resistor 53 of the collector `oftransistor develops .a positive output pulse shown at 67 in FIGURE 2.The leading edge of the output pulse 67 corresponds very closely to thepeak or la clipped input wave such as peak 69 or 62. Thus any peak ofthe input wave in excess of the clipping bias will yield an output pulsehaving a leading edge which very closely corresponds in time to such .apeak. It will be noted that the leading edge of the output pulse issomewhat later in time than the peak of the clipped wave. This is due tothe fact that the transistor 50 does not begin to conduct current untilits emitter is somewhat more positive than its base. As a result, theleading edge of the output pulse does not correspond exactly to thereference zero crossing out occurs a brief and predetermined time later.

There has been disclosed a transistor peak detector and pulse shapersuitable for use with a magnetic recording system to develop binaryoutput pulses. Circuits in accordance with the invention employtransistors as the active circuit elements .and find particular utilityin nonreturn-to-zero recording systems. The circuits are simple andreliable and permit adjustment of the clipping bias to adjust to vari usoperating conditi-ons and noise levels. The leading edge of the outputpulse closely corresponds to the peaks of the clipped input Wave.

What is claimed is:

1. A peak detector and pulse Shaper for developing sharp output pulsesin response to voltage peaks of a signal read Vfrom a movable magnet-icstorage medium to reconstitute the `binary pulses originally recordedVon the medium, said detector and pulse Shaper comprising a firsttransistor connected in the grounded collector configuration, meansincluding a first and a second resistor conected in circuit lwith theemitter of the first transistor, means connected Ito the base of thetransistor for maintainting the first transistor non-conductive in theabsence of the signal, means for applying the .signalto the base of thetlrst transistor, a second transistor connected in the grounded baseconfiguration, means -for rendering the second transistor conducting,the emitter of the second transistor being connected between the -Iirstand second resistors whereby the emitter current paths of thet-ransistor include the second resistor, an inductor .and a thirdresistor connected in parallel and in circuit with the collector of thesecond transistor, whereby the collector current of the secondtransistor is representative of the clipped peaks of the signal and adifferential voltage is developed across the inductor which isrepresentative .of the rate of Y change of the collector current, thedifferentiated voltage having a zero crossing point corresponding to thepeak of the collector current, a third emitter follower transistorcoupled to the collector ofv the second transistor, tourt-h transistormeans coupled to the emitter of the third tran- Y sistor and havingmeansfor biasing it to be non-conducting in the absence of a signal, aload impedance element connected in circuit with the collector of thefourth transistor, whereby the fourth transistor will conduct current inresponse to the differentiated voltage changing potential and develop anoutput vpulse across the load impedance element having a leading edgecorresponding substantially to the zero crossing point and hence to apeak of the detected input voltage.

2. A peak detector and pulse Shaper for developing sharp output pulsesin response tovolta'ge peaks of either polarity of a push-pull signalread from a movable mag- Vnetic storage medium to reconstitute thebinary pulses l polarity of a push-pull signal read from a Vthirdtransistor conducting,

d originally recorded on the medium, the detector and pulse Shapercomprising a rst and a second transistor, each being connected in thegrounded collector configuration, means for maintaining the firstandsecond transistors non-conductive in the absence of the signal andincluding a first resistor connected in circuit with the emitter of thefirst transistor and a second resistor connected in circuit with theemitter of the second transistor and a third resistor common to both ofthe emitter circuits, and a Voltage divider connected between the basesof the transistors, said means further including a clipping bias sourceconnected to the voltage divider, means for applying the signals inpush-pull to the bases of the first and second transistors, a thirdtransistor connected in the grounded base configuration, means forrendering .the third vtransistor conducting, the emitter of the thirdtransistor being connected between the first and the third resistor,whereby the emitter currents of the transistors dow through `the thirdresistor, two inductors and a fourth resistor connected in parallel andin circuit with the collector of the third transistor, where by thecollector current of the third transistor is re resentative of theclipped peaks of either polarity of the signal Vand a differentiatedvoltage is developed across the inductors which represents the rate ofVchange of the collector current, the dierentiated voltage having a zerocrossing point corresponding to the peak of the collector current, afourth transistor connected in the emitter follower configuration andcoupled to .the Vcollector of the third transistor, fifth and sixthtransistors connected as a differential pair and each having means riorbiasing it to be non-conducting in the absence of a signal, a loadimpedance element connected in circuit with the collector of the sixthtransistor, the sixth tran* sistor being biased so that it will conductcurrent in response to the differentiated voltage changing potential,thereby to develop an output pulse across the load irnpedance elementhavings a leading edge corresponding substantially to the zero vcrossingpoint and hence to a peak of the detected input voltage. Y

3. A peak detector and pulse Shaper for developing sharp output pulsesin response to voltage peaks ot either movable magnetic storage mediumto reconstitute the binary pulses originally recorded on the medium inaccordance with the non-return-to-zero method, the detector and pulseShaper comprising a first and a second transistor, each being conncctedin the grounded collector conguration, means for maintaining the firstand ductive in the absence of a read-out'signal and includingafirstresistor connected in circuit with the emitter of the firsttransistor' and a second resistor connected in circuit .with the emitteror the second transistor and a third resistor comm-on to both of theemitter circuits and a resistive network connected between the Vbases ofthe transistors, said means further including a clipping bias sourceconnected to the network foi-"applying a predeter-` mined clipping bias,means for applying out-of-phase relationship to the bases of the firstand second transistors, a third transistor connected `in the groundedbase configuration, means for rendering the sistor being connectedbetween the first and third resistors whereby the emitter current pathsof the transistors each include 'the third resistor, two inductors and afourth resistor connected in parallel and in circuit with thecollector-of the third transistor, whereby thecollector current of thethird transistor is representative of the clipped peaks of eitherpolarity of the signal and a differentiated voltage is developed acrossAthe inductors which corresponds to the rate `of change differentiatedvoltage havingV responding to the peak of the a zero crossing point.corcollector current, a'fourth vtransistor connected in the emitterfollower` configura-l tion and coupled to theY collector of the thirdtransistor,

second transistors non-con-V the signals in the emitter ofthe thirdtranof the collector current, the

fifth and sixth transistors coupled as a differential pair with theemitters of the fifth and sixth transistors being tied together and withthe base of the fth transistor being coupled to the emitter of thefourth transistor, a load impedance element connected in circuit withthe collector of the sixth transistor, the base of thesixth transistorbeing held at a potential with. respect to the base of the fifthtransistor so that the `sixth transistor will conduct current inresponse to the differentiated voltage changing potential and developarr output pulse across the load impedance element having a leading edgecorresponding substantially to the zero crossing point and hence to apeak ot the detected input voltage.

4. `A peak detector and pulse shaper comprising a iirst transistorconnected in the grounded collector configuration, means including iirstand second series resistors connected in circuit with the emitter of theirst transistor, means connected to the base of said iirst transistorfor maintaining the iirst transistor non-conductive in the absence ofpeaks of an input signal, means for applying an input signal includingpeaks to the base of said iirst transistor, a second transistorconnected in the grounded base configuration, said second transistorhaving its emitter connected between said iirst and second resistorswhereby the emitter current paths of said' first and second transistorsinclude said second resistor in common, means for rendering said secondtransistor conducting with the collector current thereof being therebyrepresentative of clipped peaks of said input signal, differentiatingmeans including an inductor and a resistor connected in parallel andcoupled to the collector of said second transistor for developing adifferentiated output voltage across said inductor representative of therate of change of the collector current, said output voltage having zerocrossing points corresponding to peaks of said collector current,andmeans coupled to said diterentiating'means in receiving rel-ation tosaid diierentiated output voltage for generating pulses in response toand having leading edges in coincidence with said zero crossing points.

5. A peak detector and pulse shaper for developing sharp output pulsesin response to voltage peaks of either S polarity of a push-pull inputsignal comprising lirst and second transistors each connnected in thegrounded collector contiguration, means including tirst and secondresistors respectively connected -in circuit with the emitters of saidfirst and second transistors and a third resistor common to the emittercircuits of both transistors for maintaining the transistorsnon-conductive in the absence of input signal peaks `of a given polarityand amplitude., means for applying an input signal in push-pull to thebases of said rst and second transistors, a third transistor connectedin the groundedbasel configuration, means for rendering said thirdtransistor conducting, said third transistor having its emitterconnected between said rst and third resistorsl whereby the emitterVcurrents of said iirst, second, and third transistors all ow throughsaid third resistor and the collector current of said third transistoris representative of clipped peaks of both polarities of said inputsignal, dilerentiating means including an inductor and a resistorconnected inY parallel and coupled to the collector of said thirdtransistor for developing a differentiated output voltage across saidinductor representative of the rate of change of the collector currentof said third transistor, said output voltage having Zero crossingpoints corresponding to peaks of said collector cnrrent, and meanscoupled to said differentiating means in receiving relation to saiddifferentiated output voltage for generating pulses in response to andhaving leading edges in coincidence with said zero crossing points.

References Cited by the Examiner- UNITED STATES PATENTS ARTHUR GAUSS,Primary Examiner. JOHN W. HUCKERT, Examiner.

4. A PEAK DETECTOR AND PULSE SHAPER COMPRISING A FIRST TRANSISTORCONNECTED IN THE GROUNDED COLLECTOR CONFIGURATION, MEANS INCLUDING FIRSTAND SECOND SERIES RESISTORS CONNECTED IN CIRCUIT WITH THE EMITTER OF THEFIRST TRANSISTOR, MEANS CONNECTED TO THE BASE OF SAID FIRST TRANSISTORFOR MAINTAINING THE FIRST TRANSISTOR NON-CONDUCTIVE IN THE ABSENCE OFPEAKS OF AN INPUT SIGNAL, MEANS FOR APPLYING AN INPUT SIGNAL INCLUDINGPEAKS TO THE BASE OF SAID FIRST TRANSISTOR, A SECOND TRANSISTORCONNECTED IN THE GROUNDED BASE CONFIGURATION, SAID SECOND TRANSISTORHAVING ITS EMITTER CONNECTED BETWEEN SAID FIRST AND SECOND RESISTORSWHEREBY THE EMITTER CURRENT PATHS OF SAID FIRST AND SECOND TRANSISTORSINCLUDE SAID SECOND RESISTOR IN COMMON MEANS FOR RENDERING SAID SECONDTRANSISTOR CONDUCTING WITH THE COLLECTOR CURRENT THEREOF BEING THEREBYREPRESENTATIVE OF CLIPPED PEAKS OF SAID INPUT SIGNAL, DIFFERENTIATINGMEANS INCLUDING AN INDUCTOR AND A RESISTOR CONNECTED IN PARALLEL ANDCOUPLED IN THE COLLECTOR OF SAID SECOND TRANSISTOR FOR DEVELOPING ADIFFERENTIATED OUTPUT VOLTAGE ACROSS SAID INDUCTOR REPRESENTATIVE OF THERATE OF CHANGE OF THE COLLECTOR CURRENT, SAID OUTPUT VOLTAGE HAVING ZEROCROSSING POINTS CORRESPONDING TO PEAKS OF SAID COLLECTOR CURRENT, ANDMEANS COUPLED TO SAID DIFFERENTIATING MEANS IN RECEIVING RELATION TOSAID DIFFERENTIATED OUTPUT VOLTAGE FOR GENERATING PULSES IN RESPONSE TOAND HAVING LEADING EDGES IN COINCIDENCE WITH SAID ZERO CROSSING POINTS.